I think the file you are looking for is : /drivers/spi/intel_mid_ssp_spi.c (available in yocto as a patch to kernel 3.10). But without chip documentation (at least to know if hardware support the behaviour you want) it will be difficult to modify it.
But as said Erik_van_der_Zalm it's not a bug. It's how SPI driver is operating. The large cs gap you see is result of context switch between calls, in order to reduce this gap you need to write a SPI driver for your device and not use spidev as i'm not sure it uses DMA. But with a 8bits register on your slave device you do not have any choice but use 8 bits transfers, if you use 32bits transfer it's normal for the CS line to stay low.